The present invention generally relates to the manufacture of integrated circuits and, more particularly, to the manufacture of integrated circuits having different functional areas requiring different processing and/or requiring planarizing processes.
Increased density and proximity of both active and passive electronic device structures in an integrated circuit have been recognized to provide benefits in both performance and functionality of integrated circuits. For example, reduced lengths of signal propagation paths allow operation at higher clock rates while reducing susceptibility to noise. Increased numbers of devices on a single chip also generally support such improved performance while allowing a greater number and variety of circuit functions to be provided such as local voltage regulation and conversion, local memory and additional logic circuitry or coprocessors for microprocessors, non-volatile storage, redundant circuitry, self-test arrangements and many other types and combinations of circuits. Even entire systems can be provided on a single chip for increasing numbers of applications. As an additional benefit of increased integration density, an increased number of different functional circuits generally tends to reduce the number of external connections which must be made to a given chip; a requirement which has presented substantial difficulty in many chip designs.
However, such increases in integration density and performance requires that individual electronic device structures be substantially optimized, at least in groups, in accordance with the respective functions they must perform and it is generally convenient and more economical to arrange such groups of devices in respective, differentiated areas of the chip. For example, the storage cells of a memory, collectively referred to as the array section of a memory, require very different electronic device (e.g. transistor) properties and technologies from the transistor circuits necessary to decode an address and/or carry out reading, writing and refresh operations, collectively referred to as the support section of a memory. By the same token, devices in the support section differ substantially between dynamic, static and non-volatile memory structures as well as differing substantially from devices in logic arrays, processors and the like and may operate at very different voltages and clock speeds and require much different technologies and processes to manufacture.
For DRAM cells with vertical MOSFET array devices, an array top oxide (ATO) is needed to isolate the passing word lines from active areas on the substrate. Typical processes for forming such isolating ATO areas include forming an array top oxide layer in the presence of a pad nitride layer of the DRAM. A variety of methods are known in the art for forming array top oxides and are referred to as top oxide early (TOE), top oxide nitride (TON) and top oxide late (TOL) processes.
More generally, it is common in current semiconductor manufacturing processes to use nitride (e.g. a pad nitride) to achieve certain desired shapes in semiconductor device structures and then replace the nitride with another material. Such processes are facilitated by the selectivity of some known processes which allow nitride to be selectively etched or selectively allowed to remain while etching other materials. Nitride may also be convenient since it can be used as an etch stop or polish stop in some processes. In the case of chips having vertically arranged array devices and support sections, the nitride is removed and replaced with high quality oxide in the array area to isolate the passing word line (WL) connection array from active areas on the substrate but replaced with polysilicon in the support area to form gates of the switching transistors therein. The oxide formed over the array area is referred to as an array top oxide (ATO) and its formation is relatively critical since open or short failures can be caused by a slight lack of process control, the potential for capacitive coupling and the extremely close spacing of the capacitors and the word lines and bit lines which must be formed at a similarly close spacing. The ATO can be formed either before or after the polysilicon and several different process sequences have been developed; each having certain advantages and disadvantages. A process in which the ATO is formed after formation of the polysilicon is referred to as top-oxide-late (TOL) which requires chemical-mechanical polishing to the polysilicon gates in the support areas which may compromise such structures by scratching. Another process is referred to as top-oxide-nitride (TON) in which an array top oxide area is deposited after the pad nitride has been stripped in both the array and support areas. The array top oxide is planarized. Array top oxide is then removed in the support area followed by sacrificial oxidation, support implants, gate oxidation and deposition of a gate polysilicon layer. However, the TON process results in relatively wide, open areas without polish stops which aggravates dishing during planarization as will be discussed in greater detail below. The nitride is removed simultaneously in both the array and support areas in both the TOL and TON processes. Conversely, a process in which the nitride is removed in the array area with a block mask and the ATO is formed prior to removal of nitride in the support area is referred to as top-oxide-early (TOE) but has the disadvantage that relatively more masks are required than in the TOL and TON processes.
While one lithographic exposure is invariably necessary to establish basic locations and dimensions for electronic elements to be fabricated in integrated circuits, it is also generally necessary to make at least one lithographic exposure in each differentiated functional area of a chip having a plurality of such areas. It is also necessary to make at least one, if not several, lithographic exposures to form conductors or other so-called back-end-of-line (BEOL) processes to complete a given chip design. For most of these lithographic exposures and lithographic exposures for BEOL processes, in particular, it is generally necessary and at least highly desirable to have the semiconductor structure which has been formed to that point in the manufacturing process to be highly planar in order to achieve optimal lithographic pattern resolution. Planarization is also used for other purposes such as formation of structures in trenches, isolation structures and Damascene conductors.
Planarization has been performed predominantly by mechanical polishing using a slurry of extremely fine abrasive and sometimes assisted by chemical constituents of the slurry, referred to as chemical-mechanical polishing (CMP). However, polishing processes such as CMP, while well-developed and mature, are imperfect and may cause several different types of undesirable artifacts. One type of artifact is scratching which may occur due to a relatively larger grain of abrasive or a particle broken, chipped or abraded from the wafer being polished. Scratching has become more critical in recent generations of extremely high density integrated circuit devices in which individual electronic elements are made smaller and more delicate. Scratching of insulator material and isolation structures may give rise to significant current leakage. Major portions of isolation material, transistors and memory capacitors have been observed to be physically removed by scratches. Another artifact of CMP is dishing in areas of lesser surface hardness and which can be aggravated by relatively larger areas of softer material. Dishing may be avoided in some cases by placement of areas of a hard material such as a nitride, commonly used as a preferred polish stop. However, such a strategy may be incompatible with the process requirements for a particular design such as a top oxide nitride (TON) process used in memory chip manufacture alluded to above.
In modern integrated circuits and for an array top oxide structure, in particular, good uniformity and planarity within a tolerance of 15 nm is generally required and conventional CMP processes do not meet such a stringent specification due to scratches, dishing or other artifacts. At the same time, dishing is aggravated by the topographies of differing heights in the respective array and support areas without polish stops. Further, to avoid lengthy polishing processes having increased risk of artifact production, the surface to be planarized must not exhibit severe topography and the material to be planarized must be substantially planar and of relatively uniform thickness prior to the polishing process. In summary, planarization, in general, and formation of ATO, including its planarization, in particular, is a major obstacle to obtaining acceptable manufacturing yield in high density integrated circuits having a plurality of functional areas. Current known processes have not met required tolerances for planarity of ATO and defects due to scratching damage to circuit element structures, isolation structures and insulating material surfaces.